Rtl code coverage tools

This is how we can rate the testbench and measure the simulation progress. In this case, we redefine the coverage target based on the number of days available and at the same time how best we can verify and assure that the expression will not break.

Coverage closure is an iterative process. Though code coverage is meant for improving the testbench quality, still we would be able to identify the design bugs too as part of this iterative process, as shown in the figure below.

This is how code coverage works. Where are we heading in the Semiconductor business? December 10, Sivakumar P R 0. David R. David Stamm. David Stewart. David Yao. Davorin Mista. Dawson Engler. Dean Drako.

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Naveed Sherwani. Naveen Chava. Neil Johnson. Neil Roberts. Nick Cobb. Nick Martin. In cases of low OBC coverage, we examined our test plans and modified the tests so that they resulted in activity propagating to specified points.

Usage of OBC in this manner significantly increases the chance that potential bugs will be made visible to the verification engineer. As a result of our experience with OBC, we have incorporated it into our deliverables and run it regularly.

Because it provides a more accurate measurement of the completeness of verification stimulus on the design code, OBC allows us to produce higher quality designs compared to traditional coverage tools. Functional coverage and data mining OBC is definitely a significant step forward in the coverage world. However, it is only a building block upon which we would like to create a more sophisticated coverage infrastructure. RTL is one implementation of a design specification.

In the case of our Xtensa product, for instance, the RTL implements a processor according to a certain pipelined micro-architecture. Designers tend to think at the architectural or micro-architectural level when debugging the chip, not in terms of lines of RTL.

The most obvious property in a processor is the notion of instruction. Which instructions are in which pipeline stages is critical to understanding whether the design behaves correctly or not.

More generally, coverage at this level means having a clear picture of what the processor is doing. This is where a temporal assertion language becomes handy. A hot topic today is whether a standard will be achieved soon and tools will start using temporal assertions to describe all kinds of coverage data.

In our case, we would want to define many temporal assertions corresponding to interesting architecture situations - for example, if a certain buffer is full, if some state machin e is in an interesting state, and so forth. We would then query this "database" of coverage events with sophisticated requests.

For instance, was the state machine for the Instruction Fetch module in state A when an interrupt occurred? Furthermore, under the previous scenario, was the interrupted instruction aligned on a bit boundary? Did that happen when this other buffer in the LoadStore unit was full?

Each of these properties can be expressed fairly simply using a temporal assertion language. The step of building such a coverage database and using it would mean entering the world of data mining.

Figure 3 - Cross-product coverage table This example shows how we wrote some monitors that extract coverage information and perform a cross-product between two states. The columns represent different alignment possibilities, the rows correspond to instruction classes.

The different values in the table Miss, Hit, Both, or eXecute add a third dimension to the table. We would like to generalize this concept using data mining and perform more sophisticated analysis or our micro-architectural coverage. The challenge lies in visualizing and navigating data in multi-dimensional forms, where the number of dimensions or independent variables can easily reach 5 or 6. Conclusion As design verification becomes more challenging, coverage is about to play a more central role in the verification methodology.

In the coming years, it could be expected that coverage will interface with a variety of tools such as formal engines, temporal assertion languages and data-mining tools, ultimately building what could be called the "Verification Grail. Observed coverage is a continued step in the direction of better verification technology.

It is our experience that having different ways of questioning the design, by using dif ferent approaches, is the best guarantee of finding all the bugs. Each time a new methodology offers a fresh way to challenge the design, we usually gather interesting information that had been overlooked by other methods.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse. Design And Reuse. Code coverage techniques -- a hands-on view Code coverage techniques -- a hands-on view By Alain Raynaud, EEdesign February 28, p.

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